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PIN CONNECTIONS
Table 1. 34848 Pin Definitions (continued)
A functional description of each pin can be found in the Functional Pin Description section.
Pin Number
17, 39
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
40
41
42
43
45
46
47
48
Exposed Pad
Pin Name
AGND
PLLC
ISET
GNDIO
REFIO
SCAN
VLOGIC
SYNC-OUT
DGND
DIO2
DVDD
CLK+
CLK-
DATA+
DATA-
SETUP
RESET_SCAN
LS
SHUT_B
DIO1
SYNC_IN
SYNC_PWM
VDC
SLEW
GD
COMP
CS
OUT-SW
OVP
PVCC
PGND
Pin Function
Ground
Input
Input
Input
Input
Input
Output
Ground
Formal Name
Definition
Analog ground
PLL compensation network connection
Current reference setting
Ground reference REFIO supply
Reference voltage supply
Enable scan made (‘H’ enabled, ‘L’ disabled)
Decouple for internally generated 2.5 V rail
Boost clock output
Digital ground
Data shift register I/O2
Logic supply voltage
Differential interface clock+
Differential interface clock -
Data+
Data-
SETUP input. Setup mode and clear data register when high
RESET_SCAN input. Reset internal counter
Data Latch
Shutdown pin, active low
Data shift register I/O1
Boost clock input
PWM sync input
Decouple for internal gate driver voltage
Boost driver slew rate control
Control to power switch for input voltage V IN
Boost compensation pin
Current sense input pin
FET driver output
Over-voltage protection sense pin
Switch driver power supply
Power ground
34848
Analog Integrated Circuit Device Data
4
Freescale Semiconductor
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